Semiconductor device design and process

ABSTRACT

A method for fabricating a gate-source structure for a recessed-gate static induction transistor. Source impurities are implanted prior to forming the recessed gates. The recessed gates are formed by a first isotropic etching step and a second anisotropic etching step which results in a unique overhanging protective layer used to protect the walls of the grooves during implantation of gate impurities in the bottom of the grooves. Implantations are driven and activated to form gate and source regions, the protective layer is removed and metal deposited to form electrodes. The procedure minimizes the required number of masking steps and associated mask registration problems.

BACKGROUND OF THE INVENTION

This invention relates to fabrication techniques for verticallystructured semiconductor devices and, in particular, to a recessedstructure which requires relatively simple fabrication techniques.

One example of a vertically structured semiconductor device is a staticinduction transistor (SIT) which is a field effect semiconductor devicecapable of operation at relatively high frequency and power. Thesetransistors generally have a short, high resistivity semiconductorchannel which may be controllably depleted of carriers. Thecurrent-voltage characteristics of the static induction transistor aregenerally similar to those of a vacuum tube triode. The devices aredescribed by Nishizawa et al in U.S. Pat. No. 3,828,230 issued Aug. 6,1974 and in U.S. Pat. No. 4,199,771 issued May 22, 1980.

The static induction transistor generally uses a vertical geometry withsource and drain electrodes placed on opposite sides of a thin,high-resistivity layer of one conductivity type. Gate regions of theopposite conductivity type are positioned in the high resistivity layeron opposite sides of the source. During operation a reverse bias isapplied between the gate region and the remainder of the highresistivity layer causing a depletion region to extend into the channelbelow the source. As the magnitude of the reverse bias voltage isvaried, the source-drain current and voltage derived from an attachedenergy source will also vary.

The design and fabrication of the gate-source structure ofvertical-geometry static induction transistors is difficult. In order tooperate at high frequencies and low voltages, such devices must be builtunder extremely tight dimensional control. Involved dimensions are inthe micrometer range, requiring photolithographic alignments withsubmicrometer precision. Many photolithographic steps are required todefine the device, with unnecessary steps being used to define thesource area after definition of the gate area. Similar considerationsmust be taken into account in fabricating other vertically structureddevices.

A large diversity of prior art exists in fabrication of verticalstructures for semiconductor devices. The structure of a staticinduction transistor, in particular, has been accomplished by meansincluding anisotropic etching, epitaxial regrowth, and controlledimpurity diffusion. A common characteristic of these prior methods offabricating vertically structured semiconductor devices is that contactor source impurity material is applied to the surface of thesemiconductor material after the gate regions are defined. CopendingU.S. patent application No., entitled "High Frequency Static InductionTransistor," invented by Adrian I. Cogan and assigned to the sameassignee as this application, discloses an alternate method for applyingsource impurity material prior to gate impurity material in fabricatinga static induction transistor.

SUMMARY OF THE INVENTION

The present invention relates to a method for fabricating asemiconductor device having a vertical structure, the fabrication methodusing a novel sequence of steps which provide several advantages overprior art methods and structures.

The primary novel feature of this invention is the implantation ordeposition of contact impurities prior to lithographic definition ofrecessed areas. The novel feature allows self-alignment of source andgate in static induction transistors or equivalent structures in othervertically structured semiconductor devices. A second novel feature ofthe invention allows recessed or gate definition by deposition ofimpurities such as by ion implantation after creation of a controllableoverhang in a masking level. In addition to self-aligning of the surfaceand recessed patterns, the present invention requires fewer maskingsteps, including no masking step for metallization of electrodes.

The first step of the invention is the deposition of impurities on asurface of a semiconductor material. A protective layer such as asilicon nitride or silicon dioxide masking layer is then formed on thesurface overlying the impurities. A photoresist pattern is thendeposited and windows are patterned. The protective layer is removed inthe area of the windows by a wet etching or a plasma etching process.The photoresist pattern is removed and the semiconductor materialexposed by the windows is etched to form grooves of a desired depthgreater than the width thereof. The bottoms of the grooves are also atleast as wide as the tops thereof. Impurities are then deposited at thebottom of the grooves to form regions of conductivity type opposite tothe conductivity type of the starting semiconductor material. Theremainder of the silicon nitride or silicon dioxide layer is thenstripped and metal is deposited on the stepped structure to formelectrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a high resistivity epitaxial layerof a semiconductor wafer after implantation of source impurities;

FIG. 2 is a cross-sectional view of the same epitaxial layer afteretching of gate windows in a silicon nitride or silicon dioxide layerwhich has been previously formed on the wafer.

FIG. 3 is a cross-sectional view of the same epitaxial layerillustrating initial isotropical etching to undercut the silicon nitrideor silicon dioxide layer and begin formation of the recessed gategrooves.

FIG. 4 is a cross-sectional view of the same epitaxial layerillustrating the result of anisotropical etching to deepen the recessedgate grooves and illustrating implantation of gate impurities.

FIG. 5 is a cross-sectional view of the gate-source structureillustrating gate and source regions after activation and illustratingdeposit of metal gate and source electrodes.

The Elements of the Figures are not drawn to scale and the Figures areintended only for use in explanation of fabrication steps.

DETAILED DESCRIPTION OF THE INVENTION

The invention will be described in detail with reference to a staticinduction transistor, however those skilled in the art will realize thatthe fabrication process or method described is also applicable to othervertically structured semiconductor devices as well. The invention isgenerally applicable to the fabrication of devices where it isadvantageous to vertically separate regions and contacts such as thesource and gate of a static induction transistor. The invention isapplicable to devices fabricated from a variety of semiconductormaterials such as silicon or Group III-V compounds.

A wafer, or substrate, of single crystal semiconductor material iscommonly provided as the supporting structure for fabrication of avertical-geometry semiconductor device, field-effect semiconductordevice, or static induction transistor. The substrate is commonly ofsilicon with n-type impurities and a resistivity on the order of 0.01 toten ohm-centimeters. The gate-source structure of a static inductiontransistor is formed in a thin, high resistivity epitaxial layer, with aresistivity normally greater than thirty ohm-centimeters of the sameconductivity type as the substrate grown on the upper surface of thesubstrate. The following description and the drawings relate to thegate-source structure or equivalent structure only. The underlyingsubstrate and the drain electrode commonly deposited on the undersurface of the substrate of a static induction transistor are neitherillustrated nor discussed.

FIG. 1 illustrates a fragment of a high resistivity epitaxial layer 40.The thickness of layer 40 is determined according to device applicationin accordance with known criteria, i.e., thinner for high frequencyapplications and thicker for power devices. Layer 40 may be comprised,for example of (110) orientation material where wet etching is used inthe subsequent steps of the present invention. Source impurities 42 aredeposited in the manner surface of epitaxial layer 40 which can beaccomplished, as illustrated, by ion implantation and subsequentprocessing. The implanted source impurities 42 may be, for example,arsenic and the implantation may be accompanied by conventional maskingsteps to confine implantation to a particular region of the surface ofepitaxial layer 40.

As illustrated in FIG. 2, protective layer 44 is formed on the uppersurface of epitaxial layer 40. Protective layer 44 may be of siliconnitride, Si₃ N₄, or of silicon dioxide, SiO₂. Gate windows 46 are etchedin protective layer 44 using conventional wet etching or plasma etchingand associated masking.

Recessed gate grooves 48 are then etched which can be done in twostages, as illustrated in FIG. 3 and in FIG. 4 or alternatively in asingle stage. The first stage of two stage etching is illustrated inFIG. 3 and consists of isotropical etching to both form part of thedepth of gate grooves 48 and at the same time controllably undercut apart of protective layer 44. During isotropical etching the undercut oflayer 44 will be approximately equal to the depth of the etch. Thesecond stage of etching is illustrated in FIG. 4 and consists ofanisotropically etching to form vertical gate grooves having a depthequal to that of desired gate depth. The grooves, as is illustrated,have substantially vertical side walls and a width substantially equalto the width of the groove as determined by the first stage of etching.

Alternatively, a single anisotropically etching step may be performed toform grooves 48 to the desired depth. In typical devices windows 46 willbe on the order of one to four microns wide and grooves 48 will be onthe order of five to fifteen microns deep with an aspect ratio greaterthan one and less than ten. The source islands will be on the order ofone micron to several microns wide. Grooves 48 are illustrated withvertical walls to provide separation between the source and gate regionsduring subsequent implant and metallization processing, however, thegrooves may also be trapezoidal with the bottoms wider than the tops.

FIG. 4 also illustrates deposition of impurities which can be done byion implantation of gate impurities 50. The implanted gate impurities 50may be, for example, boron. The implantation or other deposition ofimpurities requires no additional masking steps because of the overhangassociated with protective layer 44. The impurities are substantiallyconfined to the bottom surface of gate grooves 48 and to an area withinthat surface defined by the overhangs associated with protective layer44.

As illustrated in FIG. 5, when the gate and source impurities 50 and 42are implanted, they are then driven and activated using conventionalmeans to form gate regions 52 and source regions 54 in epitaxial layer40. Protective layer 44 is then removed and metal deposited byevaporation to form gate electrodes 56 and source electrodes 58, alsoillustrated in FIG. 5. No masking steps are required for the proceduresassociated with FIG. 5.

Finally, the structure may be passivated, if necessary, and bondcontacts may be opened.

During operation of the gate-source structure formed according to themethod of this invention, a time-varying reverse bias voltage is appliedto gate region 52 and the remainder of epitaxial layer 40. The depletionregion expands and contracts to vary the current and associated voltageof the channels extending from source electrodes 58 through epitaxiallayer 40 to the substrate and the drain electrode which are not shown.

I claim:
 1. A method for forming a structure for a vertically structuredsemiconductor device comprising:depositing impurities on a surface of asemiconductor material of a first conductivity type to uniformlyincrease the impurity concentration of a contact layer adjacent saidsurface sufficient to provide contact areas on said surface; forming aprotective layer over said surface; opening windows through saidprotective layer; isotropically etching grooves into said semiconductormaterial to form partial grooves underlying said windows to a depththrough said contact layer and greater than the width of said grooves;anisotropically etching to deepen said grooves beneath said windows, thebottom of each of said grooves being at least as wide as the topthereof; depositing impurities into said semiconductor material at thebottom of said grooves to form a semiconductor region of a secondconductivity type opposite said first conductivity type at the bottom ofeach of said grooves, the semiconductor regions at the bottom ofadjacent grooves forming a channel therebetween from said contact layerto a bulk region of said semiconductor material; removing saidprotective layer; and depositing metal over said surface whereby saidmetal deposits on said contact area and on the bottom of each of saidgrooves, the walls of said grooves providing isolation between the metalon said contact areas and the metal on the bottoms of said grooves.
 2. Amethod as defined in claim 1 wherein said steps of depositing impuritiesare performed by the steps of implanting ions and driving and activatingthe implanted ions.
 3. A method for forming a gate-source structure fora static induction transistor, said method comprising:forming a highresistivity epitaxial semiconductor layer; depositing source impuritieson a surface of said epitaxial layer; forming a protective layer oversaid surface; opening gate windows through said protective layer;isotropically etching said semiconductor layer to form partial gategrooves extending below said gate windows; anisotropically etching todeepen said grooves beneath said windows to a predetermined depthgreater than the width thereof, the bottom of said of said gate groovesbeing at least as wide as the top thereof; depositing gate impurities onthe bottoms of said gate grooves; removing said protective layer; anddepositing metal on said source regions and said gate regions to formsource and gate electrodes respectively.
 4. A method as defined in claim3 wherein said steps of depositing impurities are performed by the stepsof implanting ions and driving and activating the implanted ions.
 5. Amethod as defined in claim 3, wherein the ratio of the depth to width ofsaid grooves is greater than one and less than ten.
 6. A method asdefined in claim 5 wherein the depth of said grooves is in the range ofabout five to fifteen microns, the width of the semiconductor materialbetween adjacent grooves is greater than about one micron.